Lecture 7-8: System Verilog & Design Objectives for deep NN HW Accelerators
- Due No due date
- Points 8
- Questions 8
- Available after 21 Mar 2025 at 16:30
- Time limit 10 Minutes
- Allowed attempts 5
Instructions
Attention: this is a practice in-class quiz, no points will be assigned for the final grade. Enjoy!